Strained crystalline layers may be used in complementary metal-oxide-semiconductor (CMOS) devices. For example, in U.S. Patent Application Pub. No. 2004/178406A1, Chu discloses a strained crystalline layer having a tensile-strained silicon germanium (SiGe) portion and a compressive-strained SiGe portion. Alternatively, in some embodiments disclosed by Chu, the tensile-strained SiGe may instead be a tensile-strained silicon (Si) layer and the compressive-strained SiGe layer may instead be a compressive-strained germanium (Ge) layer.
According to Chu, the strained crystalline layer may be epitaxially bonded, or grown, on top of a SiGe relaxed buffer layer, such that the tensile-strained layer has a Ge concentration below that of the SiGe relaxed buffer, and the compressive-strained layer has a Ge concentration above that of the SiGe relaxed buffer. Chu explains that such a strained crystalline layer and relaxed buffer may be formed on top a semi-insulator substrate or on top of an insulating divider layer.
As disclosed by Chu, the tensile-strained layer may be suitable for hosting electron-conduction type devices, and the compressive-strained layer may be suited for hosting hole-conduction type devices. Implanted source and/or drain structures are further disclosed.